Semi-insulating polycrystalline silicon (SIPOS) is currently employed as a surface passivation material in high voltage semiconductor devices. For a discussion of the general properties of SIPOS, attention may be directed to an article by T. S. Chao, entitled "Characterization of Semi-Insulating Polycrystalline Silicon Prepared by Low Pressure Chemical Vapor Deposition," J. Electrochem. Soc., Vol. 140, No. 9, September 1993, pp 2645-2548. Because of its very high, but finite resistivity, when a SIPOS layer is formed on the top surface of a high voltage device, it has the effect of making the electric field more linear by forcing the potential of a PN junction directly beneath the SIPOS to be graded more linearly in the lateral direction (parallel to the top surface of the device); the electric field would otherwise tend to have a generally parabolic characteristic.
This ability of a SIPOS layer to reduce the lateral electric field can be used to advantage in any geometry device, including both straight and curved-geometry configurations. What is significant is the fact that a SIPOS layer affords a reduction of the lateral field in the vicinity of an underlying PN junction where the magnitude of the field is highest.
It may also be observed that, regardless of its overall geometry (e.g. straight or curved), any device will have curved edges where there is a concentration of the field. Even if it were possible to eliminate the curvature of an edge, it is still an edge, where breakdown will occur. It may be said, however, that a linear configuration has better breakdown properties than a curved configuration, since breakdown is initiated where there is a concentration of the field (in the vicinity of a departure from a linear region).
Thus, in a commonly employed symmetrically circular or cylindrical geometry device, having a center circular or disc-shaped electrode contacting a first region of the device and a second annular electrode spaced apart from and surrounding the center electrode (as in the case of respective center drain and annular source contacts of a circular DMOS FET structure), the surface area available for current flow increases with increase in radial distance from the center electrode. As a result, the radial resistance of the SIPOS layer decreases as the (radial) distance from the drain electrode increases, so that the electric field in the device beneath the SIPOS decreases as one departs from the drain electrode, or, conversely, is greater in the vicinity of the center drain electrode where curvature of the underlying PN junction is more pronounced. Thus, the device breaks down at the drain/substrate PN junction (where the electric field is highest).